SH7730 Datasheet, PDF (223/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
0000: 1-Kbyte page
0001: 4-Kbyte page
0010: 8-Kbyte page
0100: 64-Kbyte page
0101: 256-Kbyte page
0111: 1-Mbyte page
1000: 4-Mbyte page
1100: 64-Mbyte page
Note: When a value other than those listed above is recorded, operation is not guaranteed.
• V: Validity bit
Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
Not affected by a manual reset.
• PPN: Physical page number
Upper 19 bits of the physical address.
With a 1-Kbyte page, PPN[28:10] are valid.
With a 4-Kbyte page, PPN[28:12] are valid.
With a 8-Kbyte page, PPN[28:13] are valid.
With a 64-Kbyte page, PPN[28:16] are valid.
With a 256-Kbyte page, PPN[28:18] are valid.
With a 1-Mbyte page, PPN[28:20] are valid.
With a 4-Mbyte page, PPN[28:22] are valid.
With a 64-Mbyte page, PPN[28:26] are valid.
The synonym problem must be taken into account when setting the PPN (see section 7.5.5,
Avoiding Synonym Problems).
• EPR: Protection key data
6-bit data expressing the page access right as a code.
Reading, writing, and execution (instruction fetch) in privileged mode and reading, writing,
and execution (instruction fetch) in user mode can be set independently. Each bit is disabled by
0 and enabled by 1.
EPR[5]: Reading in privileged mode
EPR[4]: Writing in privileged mode
EPR[3]: Execution in privileged mode (instruction fetch)
Rev. 1.00 Sep. 19, 2007 Page 175 of 1136
REJ09B0359-0100