SH7730 Datasheet, PDF (125/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 4 Pipelining
(6-1) LDS to FPUL: 1 issue cycle
I1
I2
I3
ID s1
s2
s3
FS1 FS2 FS3 FS4 FS
(6-2) STS from FPUL: 1 issue cycle
I1
I2
I3
ID FS1 FS2 FS3 FS4
s1
s2
s3 WB
(6-3) LDS.L to FPUL: 1 issue cycle
I1
I2
I3
ID S1
S2 S3 WB
FS1 FS2 FS3 FS4 FS
(6-4) STS.L from FPUL: 1 issue cycle
I1
I2
I3
ID FS1 FS2 FS3 FS4
S1
S2
S3 WB
(6-5) LDS to FPSCR: 1 issue cycle
I1
I2
I3
ID s1
s2
s3
FS1 FS2 FS3 FS4 FS
(6-6) STS from FPSCR: 1 issue cycle
I1
I2
I3
ID FS1 FS2 FS3 FS4
s1
s2
s3 WB
(6-7) LDS.L to FPSCR: 1 issue cycle
I1
I2
I3
ID S1
S2 S3 WB
FS1 FS2 FS3 FS4 FS
(6-8) STS.L from FPSCR: 1 issue cycle
I1
I2
I3
ID FS1 FS2 FS3 FS4
S1
S2
S3 WB
(6-9) FPU load/store instruction FMOV: 1 issue cycle
I1
I2
I3
ID S1
S2 S3 WB
FS1 FS2 FS3 FS4 FS
(6-10) FLDS: 1 issue cycle
I1
I2
I3
ID
s1 s2
s3 WB
FS1 FS2 FS3 FS4 FS
(6-11) FSTS: 1 issue cycle
I1
I2
I3
ID
s1 s2
s3
FS1 FS2 FS3 FS4 FS
Figure 4.2 Instruction Execution Patterns (7)
Rev. 1.00 Sep. 19, 2007 Page 77 of 1136
REJ09B0359-0100