SH7730 Datasheet, PDF (695/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.6 FIFO
(1) Overview
The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
(2) Transfer Request
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt
sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the bits TFWM[2:0] and the bits
RFWM[2:0] in SIFCTR, respectively. Table 21.11 and table 21.12 summarize the conditions
specified by SIFCTR.
Table 21.11 Conditions to Issue Transmit Request
TFWM[2:0]
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Transmit Request
Used Areas
Empty area is 16 stages
Smallest
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more Largest
Rev. 1.00 Sep. 19, 2007 Page 647 of 1136
REJ09B0359-0100