SH7730 Datasheet, PDF (55/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 1 Overview
Item
Features
Serial I/O with
FIFO (SIOF)
• One channel
• Internal 64-byte (32 bits × 16 stages) transmit/receive FIFOs
• Supports 8-/16-bit data and 16-bit stereo audio input/output
• Sampling rate clock input from an external pin
• Incorporates a prescaler
• Module stop function
• Generation of interrupt requests and DMA transfer requests
Serial
communication
interface with
FIFO (SCIF)
• Four channels (SCIF0 to SCIF3)
• Internal 16-byte (8 bits × 16 stages) transmit/receive FIFOs
• Asynchronous mode and clock synchronous mode
• Modem control functions (RTS, CTS) on channels 2 and 3
• High-speed UART for Bluetooth
• Incorporates a prescaler
• Generation of interrupt requests and DMA transfer requests
Serial
• Two channels (SCIF4, SCIF5)
communication
interface with
• Internal 64-byte (8 bits × 64 stages) transmit/receive FIFOs
FIFO A (SCIFA) ^{• Asynchronous mode and clock synchronous mode}
• Modem control functions (RTS, CTS)
• High-speed UART for Bluetooth
• Incorporates a prescaler
IrDA interface
(IrDA)
SIM card
interface (SIM)
• Generation of interrupt requests and DMA transfer requests
• Two channels
• Conforms to version 1.2a
• One channel. Conforms to the ISO 7816-3 data protocol. (T = 0, T = 1)
• Asynchronous half-duplex character transmission protocol
• Data length: 8 bits
• Parity bit generation and check
• Selectable output clock cycles per etu (elementary time unit)
• Selectable direct convention/inverse convention
• Incorporates a prescaler
• Clock output level can be fixed (high or low) in idle state
• Generation of interrupt requests and DMA transfer requests
Rev. 1.00 Sep. 19, 2007 Page 7 of 1136
REJ09B0359-0100