SH7730 Datasheet, PDF (242/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
6. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
Rev. 1.00 Sep. 19, 2007 Page 194 of 1136
REJ09B0359-0100