SH7730 Datasheet, PDF (449/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.6 Usage Notes
(1) Reset
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All
control registers are initialized. In standby, sleep, and manual reset, control registers of the bus
state controller are not initialized. At manual reset, the current bus cycle being executed is
completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache
or if another LSI on-chip bus master module is executed when a manual reset occurs, the current
access is cancelled in longword units because the access request is cancelled by the bus master at
manual reset. If a manual reset is requested during cache fill operations, the contents of the cache
cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal
assertion, a refresh request occurs to initiate the refresh cycle. In addition, a bus arbitration
request by the BREQ signal can be accepted during manual reset signal assertion.
Some flash memories may specify a minimum time from reset release to the first access. To
ensure this minimum time, the bus state controller supports a 5-bit counter (RWTCNT). At
power-on reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up
synchronously together with CKO and an external access will not be generated until RWTCNT is
counted up to H′001F. At manual reset, RWTCNT is not cleared.
(2) Access from the CPU or FPU
In a read access to the cache from the CPU or FPU, the cache is searched. If the cache stores data,
the CPU or FPU latches the data and completes the read access. If the cache does not store data,
the CPU or FPU performs 32-byte read access to perform cache fill operations via the internal bus.
If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n
+ 2), the CPU or FPU performs 32-byte access to perform a cache fill operation on the external
interface.
For a cache-through area, the CPU or FPU performs access according to the actual access
addresses. For an instruction fetch to an even word boundary (4n), the CPU or FPU performs
longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU or FPU
performs word access.
In a write access to the cache area from the CPU or FPU, the write cycle operation differs
according to the cache write methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-
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