SH7730 Datasheet, PDF (835/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
24.3.10 Flag Clear Register (IRIF_SIR_FLG)
IRIF_SIR_FLG is a register that clears the frame error flag and EOF flag. Writing any data to the
upper or lower eight bits of this register clears the corresponding flag.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FRERC[7:0]
EOFC[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Bit
15 to 8
Bit Name
Initial
Value
FRERC[7:0] H'00
7 to 0 EOFC[7:0] H'00
R/W Description
W Frame Error Flag Clear
Writing any byte data to these bits (the upper eight bits
of the register) clears the frame error flag.
W EOF Error Flag Clear
Writing any byte data to these bits (the lower eight bits
of the register) clears the EOF error flag.
24.3.11 UART Status Register 2 (IRIF_UART_STS2)
IRIF_UART_STS2 is a register that indicates the operating status during data reception.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — IRSME IROVE IRFRE IRPRE — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R/W R/W R/W R/W R R R
Bit
15 to 7
Bit Name
—
6
IRSME
Initial
Value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive Sum Error Flag
0: No receive sum error has occurred.
1: A receive sum error has occurred.
Rev. 1.00 Sep. 19, 2007 Page 787 of 1136
REJ09B0359-0100