SH7730 Datasheet, PDF (1163/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Appendix
B. Instruction Prefetching and Its Side Effects
This LSI is provided with an internal buffer for holding pre-read instructions, and always performs
pre-reading. Therefore, program code must not be located in the last 64-byte area of any memory
space. If program code is located in these areas, a bus access for instruction prefetch may occur
exceeding the memory areas boundary. A case in which this is a problem is shown below.
Area 0
Area 1
Address
:
H'03FF FFF8
H'03FF FFFA
H'03FF FFFC
H'03FF FFFE
H'4000 0000
H'4000 0002
Instruction
:
ADD R1,R4
JMP @R2
NOP
NOP
PC (Program Counter)
Instruction prefetch address
Figure B.1 Instruction Prefetch
Figure B.1 presupposes a case in which the instruction (ADD) indicated by the program counter
(PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also
assumed that the program branches to an area other than area 1 after executing the following JMP
instruction and delay slot instruction.
In this case, a bus access (instruction prefetch) to area 1 may unintentionally occur from the
programming flow.
(1) Instruction Prefetch Side Effects
1. It is possible that an external bus access caused by an instruction prefetch may result in
misoperation of an external device, such as a FIFO, connected to the area concerned.
2. If there is no device to reply to an external bus request caused by an instruction prefetch, hang-
up will occur.
(2) Remedies
1. These illegal instruction fetches can be avoided by using the MMU.
2. The problem can be avoided by not locating program code in the last 64 bytes of any area.
Rev. 1.00 Sep. 19, 2007 Page 1115 of 1136
REJ09B0359-0100