SH7730 Datasheet, PDF (206/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value
R/W
31 to 10 VPN
Undefined R/W
9, 8

All 0
R
7 to 0 ASID
Undefined R/W
Description
Virtual Page Number
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Address Space Identifier
7.2.2 Page Table Entry Low Register (PTEL)
PTEL is used to hold the physical page number and page management information to be recorded
in the UTLB by means of the LDTLB instruction. The contents of this register are not changed
unless a software directive is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPN
Initial value: 0 0 0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPN
V SZ1 PR1 PR0 SZ0 C D SH WT
Initial value:
0
R/W: R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 29 
28 to 10 PPN
9

Initial
Value R/W
All 0
R
Undefined R/W
0
R
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Physical Page Number
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
Rev. 1.00 Sep. 19, 2007 Page 158 of 1136
REJ09B0359-0100