SH7730 Datasheet, PDF (908/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 26 A/D Converter
26.3 Register Descriptions
Table 26.2 shows the ADC module register configuration. Table 26.3 shows the register states in
each operating mode.
Table 26.2 Register Configuration
Register Name
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D control/status register
Abbreviation
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
R/W Address
Access Size
R
H'A461 0000 16
R
H'A461 0002 16
R
H'A461 0004 16
R
H'A461 0006 16
R/W H'A461 0008 16
Table 26.3 Register States in Each Operating Mode
Register
Abbreviation
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
Power-On
Reset
Initialized
Initialized
Initialized
Initialized
Initialized
Software
Standby
Initialized
Initialized
Initialized
Initialized
Initialized
Module
Standby
Initialized
Initialized
Initialized
Initialized
Initialized
Sleep
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Sep. 19, 2007 Page 860 of 1136
REJ09B0359-0100