SH7730 Datasheet, PDF (616/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
19.3.3 Compare Match Timer Counter (CMCNT)
CMCNT is a 32-bit register that is used as an up-counter.
A counter operation is set by the compare match timer control/status register (CMCSR).
Therefore, set CMCSR first, before starting a channel operation corresponding to the compare
match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS
bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data
that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are
initialized to H'00000000.
19.3.4 Compare Match Timer Constant Register (CMCOR)
CMCOR is a 32-bit register that sets the compare match period with CMCNT.
When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this
register become valid. When the register should be written to, write the data that is added H'0000
to the upper half in a 32-bit operation.
An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The
contents of this register are initialized to H'FFFFFFFF.
Rev. 1.00 Sep. 19, 2007 Page 568 of 1136
REJ09B0359-0100