SH7730 Datasheet, PDF (347/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.4.3 CSn Space Wait Control Register (CSnWCR)
This register specifies various wait cycles for memory accesses. The bit configuration of this
register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or
TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before
accessing the target area. Specify CSnBCR first, then specify CSnWCR.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
(1) Normal Space and Byte-Selection SRAM
• CS0WCR, CS6AWCR, CS6BWCR
Bit: 31 30
——
Initial value: 0
0
R/W: R R
Bit: 15 14
ADR
SFIX
—
Initial value: 0
0
R/W: R/W R
29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — BAS —
WW[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R R R R/W R R/W R/W R/W
13 12 11 10 9
8
7
6
5
4
3
2
1
0
— SW[1:0]
WR[3:0]
WM — — — — HW[1:0]
0
0
0
1
0
1
0
1
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn and RDWR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RDWR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RDWR signal at the write
timing.
19

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 299 of 1136
REJ09B0359-0100