SH7730 Datasheet, PDF (1111/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
33.4.2 Control Signal Timing
Table 33.8 Control Signal Timing
Conditions: V_CCQ = 3.0 to 3.6 V, V_CC = 1.1 to 1.3 V, T_a = -20 to 75°C
Item
Symbol Min.
Max.
Unit
Figure
RESETP pulse width
t
RESPW
1*²

ms
33.4
BREQ setup time
BREQ hold time
t
BREQS
t_BREQH
1/2t + 7
cyc

1/2t_cyc + 2

ns
33.6
ns
NMI setup time*¹
t_NMIS
8

ns
33.5
NMI hold time
t_NMIH
3

ns
IRQ7 to IRQ0 setup time*¹
t
8
IRQS

ns
IRQ7 to IRQ0 hold time
t
3
IRQH

ns
BACK delay time
t
BACKD

1/2t + 13 ns
cyc
33.6
Bus tri-state delay time 1
t
0
BOFF1
30
ns
33.6
Bus tri-state delay time 2
t_BOFF2
0
30
ns
33.7
Bus buffer on time 1
t
0
BON1
30
ns
Bus buffer on time 2
t_BON2
0
30
ns
Notes: 1. NMI, and IRQ7 to IRQ0 are asynchronous. Changes are detected at the clock rise
when the setup time shown is used. If the setup time cannot be used, detection may be
delayed until the next clock rises.
2. In standby mode, t_RESPW = t_OSC (10 ms).
3. t_cyc means the external bus clock (Bφ) cycle time.
RESETP
t_RESPW
Figure 33.4 Reset Input Timing
Rev. 1.00 Sep. 19, 2007 Page 1063 of 1136
REJ09B0359-0100