SH7730 Datasheet, PDF (322/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.6 Interrupt Response Time
Table 10.8 shows the interrupt response time, which is the interval from when an interrupt request
occurs until the interrupt exception handling is started and the start instruction of the exception
handling routine is fetched.
Table 10.8 Interrupt Response Time
Number of States
Item
NMI
IRQ
Peripheral Module Remarks
Priority determination time 5 Bcyc + 2 Pcyc 4 Bcyc + 2 Pcyc 5 Pcyc
Wait time until the CPU
finishes the current sequence
S - 1 (≥ 0) × Icyc
Interval from when interrupt
exception handling begins
(saving SR and PC) until an
SuperHyway bus request is
issued to fetch the start
instruction of the exception
handling routine
11 Icyc + 1 Scyc
Response time Total
(S + 10) Icyc +
1 Scyc + 5 Bcyc +
2 Pcyc
(S + 10) Icyc +
1 Scyc + 4 Bcyc +
2 Pcyc
(S + 10) Icyc +
1 Scyc + 5 Pcyc
Minimum 18 Icyc + S × Icyc
17 Icyc + S × Icyc
16 Icyc + S × Icyc
When
Icyc:Scyc:Bcyc:
Pcyc = 1:1:1:1
[Legend]
Icyc: Period for one CPU clock cycle
Scyc: Period for one SH clock cycle
Bcyc: Period for one bus clock cycle
Pcyc: Period for one peripheral clock cycle
S: Number of instruction execution states
Rev. 1.00 Sep. 19, 2007 Page 274 of 1136
REJ09B0359-0100