SH7730 Datasheet, PDF (108/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Instruction
Operation
DIV0S
DIV0U
Rm,Rn
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0 → M/Q/T
DMULS.L Rm,Rn
Signed,
Rn × Rm → MAC,
32 × 32 → 64 bits
DMULU.L Rm,Rn
DT
Rn
Unsigned,
Rn × Rm → MAC,
32 × 32 → 64 bits
Rn – 1 → Rn;
when Rn = 0, 1 → T
When Rn ≠ 0, 0 → T
EXTS.B Rm,Rn
Rm sign-extended from
byte → Rn
EXTS.W Rm,Rn
Rm sign-extended from
word → Rn
EXTU.B Rm,Rn
Rm zero-extended from
byte → Rn
EXTU.W Rm,Rn
Rm zero-extended from
word → Rn
MAC.L
@Rm+,@Rn+
Signed,
(Rn) × (Rm) + MAC → MAC
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
MAC.W
MUL.L
@Rm+,@Rn+
Signed,
(Rn) × (Rm) + MAC → MAC
Rn + 2 → Rn,
Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
MULS.W Rm,Rn
Signed,
Rn × Rm → MACL
16 × 16 → 32 bits
MULU.W Rm,Rn
NEG
Rm,Rn
Unsigned,
Rn × Rm → MACL
16 × 16 → 32 bits
0 – Rm → Rn
NEGC
Rm,Rn
0 – Rm – T → Rn,
borrow → T
SUB
Rm,Rn
Rn – Rm → Rn
Instruction Code
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
Privileged T Bit
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Calculation
result
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0
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Comparison
result
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Borrow
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Rev. 1.00 Sep. 19, 2007 Page 60 of 1136
REJ09B0359-0100