SH7730 Datasheet, PDF (334/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Table 11.4 Address Space Map 3 (CMNCR.MAP[1:0] = B'10)
Physical Address
Area
Memory to be Connected
Capacity
H'00000000 to H'03FFFFFF Area 0 Normal memory
64 Mbytes
H'04000000 to H'07FFFFFF
H'08000000 to H'0FFFFFFF
Burst ROM (Asynchronous)
Area 1
Internal I/O register area*²
Area 2/3*³ Normal memory
64 Mbytes
128 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to H'13FFFFFF Area 4
Normal memory
Byte-selection SRAM
64 Mbytes
Burst ROM (Asynchronous)
H'14000000 to H'15FFFFFF Area 5A Normal memory
32 Mbytes
H'16000000 to H'17FFFFFF Area 5B Normal memory
32 Mbytes
Byte-selection SRAM
H'18000000 to H'19FFFFFF Area 6A Normal memory
32 Mbytes
H'1A000000 to H'1BFFFFFF Area 6B Normal memory
32 Mbytes
H'1C000000 to H'1FFFFFFF Area 7
Byte-selection SRAM
Reserved area*¹
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. Set the top three bits of the address to 101 to allocate in the P2 space.
3. For the merged area of areas 2 and 3, registers CS3BCR and CS3WCR are valid and
CS6B is valid as the chip select signal.
Rev. 1.00 Sep. 19, 2007 Page 286 of 1136
REJ09B0359-0100