SH7730 Datasheet, PDF (851/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
(3) Data Reception Timing
Figure 24.4 shows the data reception timing controlled by the UART.
When the last stop bit of the received data is detected, the received data is stored and the receive
flags are set or cleared appropriately.
Basic clock for
reception
Control register
(reception)
During reception of one unit of data
During reception of
one unit of data
RXD
Receive buffer full
flag (status)
Receive buffer full
flag (interrupt)
Receive parity error
flag (status)
Receive framing
error flag (status)
Receive overrun
error flag (status)
Receive sum error
flag (status)
Receive sum error
flag (interrupt)
Data reception
enabled
Start bit checked
Interrupt mask cleared
Stop bit
detected
Start bit
checked
Receive data register read
Note:
The data reception control circuit recognizes the start bit when a falling edge is detected on the RXD input pin.
After that, the control circuit samples the signal level at the center of the start bit duration, and if a low level is
detected on the RXD input pin, the control circuit starts the reception sequence.
Figure 24.4 Data Reception Timing
Rev. 1.00 Sep. 19, 2007 Page 803 of 1136
REJ09B0359-0100