SH7730 Datasheet, PDF (665/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
9
TXE
0
R/W Transmit Enable
0: Disables data transmission from the SIOFTXD pin
1: Enables data transmission from the SIOFTXD pin
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according to
the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOFTXD pin begins.
This bit is initialized upon a transmit reset.
8
RXE
0
R/W Receive Enable
0: Disables data reception from SIOFRXD
1: Enables data reception from SIOFRXD
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOFRXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
This bit is initialized upon receive reset.
7 to 2 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 617 of 1136
REJ09B0359-0100