SH7730 Datasheet, PDF (310/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.4 Interrupt Sources
There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip peripheral modules.
Each interrupt has a priority level (16 to 0), with 1 the lowest and 16 the highest. Priority level 0
masks an interrupt, so the interrupt request is ignored.
10.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. When the BL bit in SR of the CPU is 0,
NMI interrupts are always accepted. In sleep or software standby mode, NMI interrupts are
accepted regardless of the BL setting. In addition, NMI interrupts are accepted by setting the
NMIB bit in ICR0 regardless of the BL setting.
The NMI signal is edge-detected. The NMIE bit in ICR0 is used to select either rising or falling
edge detection. After the NMIE bit in ICR0 is modified, NMI interrupts are not detected for a
maximum of six bus clock cycles.
NMI interrupt exception handling does not affect the interrupt mask level (IMASK) in SR.
10.4.2 IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. When level-sensing is selected for IRQ
interrupts by the IRQnS bits (n = 7 to 0) in ICR1, the pin levels must be retained until the CPU
accepts the interrupts and starts interrupt handling.
When the LSH bit of ICR0 is 0, if an interrupt request is canceled before the CPU accepts it, the
INTC holds the interrupt request until the CPU accepts another interrupt. The interrupt held in the
INTC can be cleared by setting the corresponding interrupt mask bit (IMR bit in the interrupt
mask register) to 1. The LSH bit should normally be set to 1.
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level of the accepted interrupt. When the INTMU bit is cleared to 0,
the IMASK value in SR is not affected by the accepted interrupt.
Rev. 1.00 Sep. 19, 2007 Page 262 of 1136
REJ09B0359-0100