SH7730 Datasheet, PDF (480/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Channel 0 becomes bottom
priority
CH1 > CH2 > CH3 > CH4 > CH5 > CH0
(2) When channel 1 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
CH2 > CH3 > CH4 > CH5 > CH0 > CH1
Channel 1 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 1, is also
shifted.
(3) When channel 2 transfers
Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Priority order
after transfer
CH3 > CH4 > CH5 > CH0 > CH1 > CH2
Post-transfer priority order
when there is an
immediate transfer
request to channel 5 only
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
after there is a request to transfer
channel 5 only, channel 5 becomes
bottom priority and the priority of
channels 3 and 4, which were
higher than channel 5, are also
shifted.
(4) When channel 5 transfers
Initial priority order _{CH0 > CH1 > CH2 > CH3 > CH4 > CH5}
Priority order does not change.
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Figure 12.2 Round-Robin Mode
Rev. 1.00 Sep. 19, 2007 Page 432 of 1136
REJ09B0359-0100