SH7730 Datasheet, PDF (460/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.6 DMA Transfer Count Registers (TCRB_0 to TCRB_3)
TCRB are 32-bit readable/writable registers. Data to be written from the CPU to TCR is also
written to TCRB. While the half end function is used, TCRB are used as the initial value hold
registers to detect a half end. Also, TCRB specify the number of DMA transfers which are set in
TCR in repeat mode. TCRB specify the number of DMA transfers and are used as transfer count
counters in reload mode.
In reload mode, the lower 16 bits operate as transfer count counters, values of SAR and DAR are
updated after the value of the lower 16 bits became 0, and then the value of the upper 16 bits of
TCRB are loaded to the lower 16 bits. In upper 16 bits, set the number of transfers which starts
reloading. In reload mode, the same number of transfers should be set in both upper and lower 16
bits. Also, set the HIE bit in CHCR to 0 and do not use the half end function.
For details on the half end function, see section 12.4.5, Repeat Mode Transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCRB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCRB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 412 of 1136
REJ09B0359-0100