SH7730 Datasheet, PDF (1043/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
30.3 Operation Description
30.3.1 Definition of Words Related to Accesses
"Instruction fetch" refers to an access in which an instruction is fetched. For example, fetching the
instruction located at the branch destination after executing a branch instruction is an instruction
access. "Operand access" refers to any memory access accompanying execution of an instruction.
For example, accessing an address (PC + disp × 2 + 4) in the instruction MOV.W@(disp,PC),Rn
is an operand access. "Data" is used in contrast to "address".
All types of operand access are classified into read or write access. Special care must be taken in
using the following instructions.
• PREF, OCBP, and OCBWB: Instructions for a read access
• MOVCA.L and OCBI: Instructions for a write access
• TAS.B: Instruction for a single read access or a single write access
The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions is access
without the data value; therefore, do not include the data value in the match conditions for these
instructions.
The operand size should be defined for all types of operand access. Available operand sizes are
byte, word, longword, and quadword. For operand access accompanying the PREF, OCBP,
OCBWB, MOVCA.L, and OCBI instructions, the operand size is defined as longword.
30.3.2 User Break Operation Sequence
The following describes the sequence from when the break condition is set until the user break
exception handling is initiated.
1. Specify the operand size, bus, instruction fetch/operand access, and read/write as the match
conditions using the match condition setting register (CBR0 or CBR1). Specify the break
address using the match address setting register (CAR0 or CAR1), and specify the address
mask condition using the match address mask setting register (CAMR0 or CAMR1). To
include the ASID in the match conditions, set the AIE bit in the match condition setting
register and specify the ASID value by the AIV bit in the same register. To include the data
value in the match conditions, set the DBE bit in the match condition setting register; specify
the break data using the match data setting register (CDR1); and specify the data mask
condition using the match data mask setting register (CDMR1). To include the execution
count in the match conditions, set the ETBE bit of the match condition setting register; and
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