SH7730 Datasheet, PDF (107/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Instruction
Operation
Instruction Code
Privileged T Bit
SWAP.W Rm,Rn
Rm → swap upper/lower 0110nnnnmmmm1001
—
—
words → Rn
XTRCT
Rm,Rn
Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101
—
—
Note: * The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the
displacement (disp).
Table 3.5 Arithmetic Operation Instructions
Instruction
Operation
ADD
Rm,Rn Rn + Rm → Rn
ADD
#imm,Rn Rn + imm → Rn
ADDC
Rm,Rn
Rn + Rm + T → Rn,
carry → T
ADDV
Rm,Rn
Rn + Rm → Rn,
overflow → T
CMP/EQ #imm,R0 When R0 = imm, 1 → T
Otherwise, 0 → T
CMP/EQ Rm,Rn
When Rn = Rm, 1 → T
Otherwise, 0 → T
CMP/HS Rm,Rn
When Rn ≥ Rm (unsigned),
1→T
Otherwise, 0 → T
CMP/GE Rm,Rn
When Rn ≥ Rm (signed),
1→T
Otherwise, 0 → T
CMP/HI
Rm,Rn
When Rn > Rm (unsigned),
1→T
Otherwise, 0 → T
CMP/GT Rm,Rn
When Rn > Rm (signed),
1→T
Otherwise, 0 → T
CMP/PZ Rn
When Rn ≥ 0, 1 → T
Otherwise, 0 → T
CMP/PL Rn
When Rn > 0, 1 → T
Otherwise, 0 → T
CMP/STR Rm,Rn
When any bytes are equal,
1→T
Otherwise, 0 → T
DIV1
Rm,Rn 1-step division (Rn ÷ Rm)
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010001
0100nnnn00010101
0010nnnnmmmm1100
0011nnnnmmmm0100
Privileged T Bit
—
—
—
—
—
Carry
—
Overflow
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Comparison
result
—
Calculation
result
Rev. 1.00 Sep. 19, 2007 Page 59 of 1136
REJ09B0359-0100