SH7730 Datasheet, PDF (813/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Start of reception
Set receive trigger number in
RTRG[1:0] in SCAFCR
1
Set RFRST bit in SCAFCR to 1 ₂
Clear RFRST bit in SCAFCR to 0
Wait
3
1-bit interval elapsed?
No
Yes
Set RE bit in SCASCR
When using receive FIFO data interrupt, 4
set RIE bit to 1
1. Set the receive trigger number
in SCAFCR.
2. Reset the receive FIFO.
3. Wait for one bit interval.
4. Reception is started when the RE
bit in SCASCR is set to 1.
5. Read receive data while the RDF
bit is 1.
6. After the end of reception, clear the
RE bit to 0.
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCAFRDR
5
Clear RE bit in SCASCR to 0
6
End of reception
Figure 23.19 Sample Serial Reception Flowchart (2)
(Second and Subsequent Reception)
Rev. 1.00 Sep. 19, 2007 Page 765 of 1136
REJ09B0359-0100