SH7730 Datasheet, PDF (1044/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
specify the execution count using the execution count break register (CETR1). To use the
sequential break, set the MFE bit of the match condition setting register; and specify the
number of the first channel using the MFI bit.
2. Specify whether or not to request a break when the match condition is satisfied and the break
timing when the match condition is satisfied as a result of fetching the instruction using the
match operation setting register (CRR0 or CRR1). After having set all the bits in the match
condition setting register except the CE bit and the other necessary registers, set the CE bit and
read the match condition setting register again. This ensures that the set values in the control
registers are valid for the subsequent instructions immediately after reading the register.
Setting the CE bit of the match condition setting register in the initial state after reset via the
control registers may cause an undesired break.
3. When the match condition has been satisfied, the corresponding condition match flag (MF1 or
MF0) in the channel match flag register (CCMFR) is set. A break is also requested to the CPU
according to the set values in the match operation setting register (CRR0 or CRR1). The CPU
operates differently according to the BL bit value of the SR register: when the BL bit is 0, the
CPU accepts the break request and executes the specified exception handling; and when the
BL bit is 1, the CPU does not execute the exception handling.
4. The match flags (MF1 and MF0) can be used to confirm whether or not the corresponding
match condition has been satisfied. Although the flag is set when the condition is satisfied, it
is not cleared automatically; therefore, write 0 to the flag bit by issuing a memory store
instruction to the channel match flag register (CCMFR) in order to use the flag again.
5. Breaks may occur virtually at the same time for channels 0 and 1. In this case, only one break
request is sent to the CPU; however, the two condition match flags corresponding to these
breaks may be set.
6. While the BL bit in the SR register is 1, no break requests are accepted. However, whether or
not the condition has been satisfied is determined. When the condition is determined to be
satisfied, the corresponding condition match flag is set.
7. If the sequential break conditions are set, the condition match flag is set every time the match
conditions are satisfied for each channel. When the conditions have been satisfied for the first
channel in the sequence but not for the second channel in the sequence, clear the condition
match flag for the first channel in the sequence in order to release the first channel in the
sequence from the match state.
30.3.3 Instruction Fetch Cycle Break
1. If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the
instruction fetch cycle is handled as a match condition. To request a break upon satisfying the
match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the
corresponding channel. Either before or after executing the instruction can be selected as the
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