SH7730 Datasheet, PDF (673/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
9
RFFUL
0
R
Receive FIFO Full
0: Receive FIFO not full
1: Receive FIFO full
• This bit is valid when the RXE bit in SICTR is 1.
• This bit indicates a state; if SIRDR is read, the SIOF
clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
8
RDREQ 0
R
Receive Data Transfer Request
0: Indicates that the size of valid area in the receive
FIFO does not exceed the size specified by the
RFWM bit in SIFCTR.
1: Indicates that the size of valid area in the receive
FIFO exceeds the size specified by the RFWM bit in
SIFCTR.
A receive data transfer request is issued when the valid
data area in the receive FIFO exceeds the size
specified by the RFWM bit in SIFCTR.
When using receive data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, the SIOF again indicates 1 for this bit.
• This bit is valid when the RXE bit in SICTR is 1.
• This bit indicates a state; if the size of valid data
area in the receive FIFO is less than the size
specified by the RFWM bit in SIFCTR, the SIOF
clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
7, 6
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 625 of 1136
REJ09B0359-0100