SH7730 Datasheet, PDF (528/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
After the interrupt, interrupt exception handling is executed and a code indicating the interrupt
source is set in INTEVT. Interrupts are accepted in software standby mode even when the BL bit
in SR is 1. If necessary, save the SPC and SSR on the stack before executing the SLEEP
instruction.
Immediately after the SLEEP instruction, clock output via the CKO pin is halted until exit from
software standby mode
When restarting the internal crystal oscillator, set OSCWTCR of the CPG to ensure the oscillation
settling time.
(b) Exit Driven by a Reset
Exit from software standby mode is triggered by a power-on reset or a system reset.
14.4.4 Module Standby Mode
(1) Transition to Module Standby Mode
Setting the MSTP bits in the module stop registers to 1 halts the supply of clocks to the
corresponding on-chip peripheral modules. This function can be used to reduce power
consumption in normal mode.
Modules in module standby mode keep the state immediately before the transition to the module
standby mode. The registers keep the contents before halted, and the external pins keep the
functions before halted. At waking up from the module standby state, operation is restarted from
the condition immediately before the registers and external pins have halted.
Note: Make sure to set the MSTP bit to 1 while the modules have completed the operation and
are in an idle state, with no interrupt sources from the external pins or other modules.
(2) Exit from Module Standby Mode
Exit from module standby mode is triggered by clearing the respective MSTP bit to 0.
Rev. 1.00 Sep. 19, 2007 Page 480 of 1136
REJ09B0359-0100