SH7730 Datasheet, PDF (35/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Figure 21.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 657
Figure 21.15 Transmit and Receive Timing (16-Bit Monaural Data)......................................... 657
Figure 21.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 658
Figure 21.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 658
Figure 21.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 659
Figure 21.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 659
Figure 21.20 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 660
Section 22 Serial Communication Interface with FIFO (SCIF)
Figure 22.1 Block Diagram of SCIF........................................................................................... 663
Figure 22.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits) ............................................................ 693
Figure 22.3 Sample Flowchart for SCIF Initialization ............................................................... 695
Figure 22.4 Sample Flowchart for Transmitting Serial Data ...................................................... 696
Figure 22.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit) ............................ 698
Figure 22.6 Example of Operation Using Modem Control (CTS).............................................. 698
Figure 22.7 Sample Flowchart for Receiving Serial Data .......................................................... 699
Figure 22.8 Sample Flowchart for Receiving Serial Data (cont)................................................ 700
Figure 22.9 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit)..................... 702
Figure 22.10 Example of Operation Using Modem Control (RTS)............................................ 702
Figure 22.11 Data Format in Clock Synchronous Communication ............................................ 703
Figure 22.12 Sample Flowchart for SCIF Initialization.............................................................. 704
Figure 22.13 Sample Flowchart for Transmitting Serial Data .................................................... 705
Figure 22.14 Example of SCIF Transmit Operation................................................................... 706
Figure 22.15 Sample Flowchart for Receiving Serial Data (1)................................................... 707
Figure 22.16 Sample Flowchart for Receiving Serial Data (2)................................................... 708
Figure 22.17 Example of SCIF Receive Operation .................................................................... 708
Figure 22.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 709
Figure 22.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 712
Section 23 Serial Communication Interface with FIFO A (SCIFA)
Figure 23.1 Block Diagram of SCIFA........................................................................................ 717
Figure 23.2 Sample SCIFA Initialization Flowchart .................................................................. 748
Figure 23.3 Sample Serial Transmission Flowchart ................................................................... 749
Figure 23.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 751
Figure 23.5 Example of Transmit Data Stop Function ............................................................... 751
Figure 23.6 Transmit Data Stop Function Flowchart ................................................................. 752
Figure 23.7 Sample Serial Reception Flowchart (1)................................................................... 753
Figure 23.8 Sample Serial Reception Flowchart (2)................................................................... 754
Rev. 1.00 Sep. 19, 2007 Page xxxv of xlviii