SH7730 Datasheet, PDF (552/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
Initial
Bit
Bit Name Value R/W Description
1
TG1EB
0
R/W TPUn_TGR Interrupt Enable B
When the TGFB bit in TPUn_TSR is set to 1 (a
compare match between TPUn_TCNT and
TPUn_TGRB has occurred), this bit enables or disables
interrupt requests corresponding to the state of the
TGFB flag.
0: Interrupt requests by TCFB flag disabled
1: Interrupt requests by TCFB flag enabled
0
TG1EA
0
R/W TPUn_TGR Interrupt Enable A
When the TGFA bit in TPUn_TSR is set to 1 (a
compare match between TPUn_TCNT and
TPUn_TGRA has occurred), this bit enables or disables
interrupt requests corresponding to the state of the
TGFA flag.
0: Interrupt requests by TCFA flag disabled
1: Interrupt requests by TCFA flag enabled
16.4.5 Timer Status Registers (TPUn_TSR)
TPUn_TSR displays information on the state of each channel. The TPU has one TPUn_TSR
register for each channel. TPUn_TSR is initialized to H'0000 by a reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — — TCFV TGFD TGFC TGFB TGFA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Initial
Bit
Bit Name Value R/W
15 to 5 
All 0 R
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 1.00 Sep. 19, 2007 Page 504 of 1136
REJ09B0359-0100