SH7730 Datasheet, PDF (338/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
CKO CKO
STP DRV
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— BSD MAP[1:0] BLOCK DPRTY[1:0] —
—
—
—
—
END
IAN
—
HIZ HIZ
MEM CNT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1 0/1* 0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 26 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
25
CKOSTP 0
R/W CKO Stop
0: Outputs CKO.
1: Stops CKO and outputs a low level.
Note: Just after the CKOSTP bit has been set to 1, an
invalid waveform may be output as the CKO
signal before it becomes stable at low level.
24
CKODRV 0
R/W CKO, CKE Drive Control
Controls the operation selected by bit 0 (HIZCNT)
setting. See bit 0 (HIZCNT) for details.
23 to 15 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 290 of 1136
REJ09B0359-0100