SH7730 Datasheet, PDF (228/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Figure 7.15 is a flowchart of memory access using the ITLB in TLB extended mode.
VA is
in P4 area
Instruction access to virtual address (VA)
VA is
in P2 area
VA is
in P1 area
CCR.ICE?
0
1
VA is in P0, U0,
or P3 area
MMUCR.AT = 1
No
Yes
Hardware ITLB
miss handling
Search UTLB
Record in ITLB ^{Yes Match?}
No
No
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
No
VPNs match
and V = 1
Yes
Yes
No
VPNs match,
ASIDs match, and
V=1
Yes
No
Only one
entry matches
Yes
Instruction TLB
miss exception
Instruction TLB
multiple hit exception
0 (User)
ICBI or normal instruction access?
ICBI
Normal instruction access
EPR[2] = 0 and ^Yes
EPR[0] = 0
No
0
EPR[0]?
1
SR.MD?
1 (Privileged)
ICBI or normal instruction access?
ICBI
Normal instruction access
Yes _{EPR[5] = 0 and}
EPR[3] = 0
No
0
EPR[3]?
1
Instruction TLB protection
violation exception
No
C = 1 and
CCR.ICE = 1
Yes
Internal resource access
Memory access
(Non-cacheable)
Cache access
Figure 7.15 Flowchart of Memory Access Using ITLB (TLB Extended Mode)
Rev. 1.00 Sep. 19, 2007 Page 180 of 1136
REJ09B0359-0100