SH7730 Datasheet, PDF (1063/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 31 User Debugging Interface (H-UDI)
31.3 Register Descriptions
The H-UDI has the following registers.
Table 31.2 Register Configuration (1)
CPU Side
Register Name
Area P4
Abbreviation R/W Address*¹
Initial
Area 7 Address*¹ Size Value*²
Instruction register
SDIR
R
H'FC11 0000
H'1C11 0000
16 H'0EFF
Data register H
SDDR/SDDRH R/W H'FC11 0008
H'1C11 0008
32/16 Undefined
Data register L
SDDRL
R/W H'FC11 000A
H'1C11 000A
16 Undefined
Interrupt source register SDINT
R/W H'FC11 0018
H'1C11 0018
16 H'0000
Bypass register
SDBPR




Undefined
Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual
address space. The area 7 address is an address when accessing through area 7 in a
physical space using the TLB.
2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
initializes to these values.
Table 31.3 Register Configuration (2)
H-UDI Side
Register Name
Abbreviation R/W
Size
Initial Value*¹
Instruction register
SDIR
R/W
32
H'FFFF FFFD (fixed value*²)
Data register H
SDDR/SDDRH 


Data register L
SDDRL



Interrupt source register SDINT
W*³
32
H'0000 0000
Bypass register
SDBPR
R/W
1
Undefined
Notes: 1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
initializes to these values.
2. When reading via the H-UDI, the value is always H'FFFF FFFD.
3. Only 1 can be written to the LSB by the H-UDI interrupt command.
Rev. 1.00 Sep. 19, 2007 Page 1015 of 1136
REJ09B0359-0100