SH7730 Datasheet, PDF (15/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

12.3 Register Descriptions........................................................................................................ 406
12.3.1 DMA Source Address Registers (SAR_0 to SAR_5) ............................................ 409
12.3.2 DMA Source Address Registers (SARB_0 to SARB_3) ....................................... 410
12.3.3 DMA Destination Address Registers (DAR_0 to DAR_5).................................... 410
12.3.4 DMA Destination Address Registers (DARB_0 to DARB_3)............................... 411
12.3.5 DMA Transfer Count Registers (TCR_0 to TCR_5) ............................................. 411
12.3.6 DMA Transfer Count Registers (TCRB_0 to TCRB_3) ........................................ 412
12.3.7 DMA Channel Control Registers (CHCR_0 to CHCR_5)..................................... 413
12.3.8 DMA Operation Register (DMAOR)..................................................................... 421
12.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2) .............................. 423
12.4 Operation .......................................................................................................................... 427
12.4.1 DMA Transfer Requests......................................................................................... 427
12.4.2 Channel Priority ..................................................................................................... 431
12.4.3 DMA Transfer Types ............................................................................................. 434
12.4.4 DMA Transfer Flow............................................................................................... 441
12.4.5 Repeat Mode Transfer............................................................................................ 443
12.4.6 Reload Mode Transfer............................................................................................ 444
12.4.7 DREQ Pin Sampling Timing.................................................................................. 445
12.5 Usage Notes ...................................................................................................................... 448
12.5.1 DMA Transfer for Peripheral Modules .................................................................. 448
12.5.2 Module Stop........................................................................................................... 448
12.5.3 Address Error ......................................................................................................... 448
12.5.4 Notes on Burst Mode Transfer ............................................................................... 448
Section 13 Clock Pulse Generator (CPG)..........................................................449
13.1 Features............................................................................................................................. 449
13.2 Input/Output Pins.............................................................................................................. 452
13.3 Clock Operating Modes .................................................................................................... 453
13.4 Register Descriptions........................................................................................................ 453
13.4.1 Frequency Control Register (FRQCR)................................................................... 454
13.4.2 PLL Control Register (PLLCR) ............................................................................. 456
13.4.3 IrDA Clock Control Register (IrDACLKCR) ........................................................ 457
13.4.4 Oscillation Settling Time Watch Timer Control Register (OSCWTCR) ............... 459
13.5 Changing Frequency ......................................................................................................... 461
13.5.1 Changing Multiplication Ratio of PLL Circuit ...................................................... 461
13.5.2 Changing Division Ratio........................................................................................ 461
13.5.3 Changing Clock Operating Mode .......................................................................... 461
13.5.4 Turning On/Off of PLL Circuit .............................................................................. 461
13.6 Procedure for Ensuring the Internal Oscillator Settling Time on Exit from
Software Standby Mode.................................................................................................... 462
Rev. 1.00 Sep. 19, 2007 Page xv of xlviii