SH7730 Datasheet, PDF (668/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.4 Receive Data Register (SIRDR)
SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the
receive FIFO.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRDL[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SIRDR[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 16 SIRDL
[15:0]
15 to 0 SIRDR
[15:0]
Initial
Value R/W
Undefined R
Undefined R
Description
Left-Channel Receive Data
Store data received from the SIOFRXD pin as left-
channel data. The position of the left-channel data in
the receive frame is specified by the RDLA bit in
SIRDAR.
• These bits are valid only when the RDLE bit in
SIRDAR is set to 1.
Right-Channel Receive Data
Store data received from the SIOFRXD pin as right-
channel data. The position of the right-channel data in
the receive frame is specified by the RDRA bit in
SIRDAR.
• These bits are valid only when the RDRE bit in
SIRDAR is set to 1.
Rev. 1.00 Sep. 19, 2007 Page 620 of 1136
REJ09B0359-0100