SH7730 Datasheet, PDF (722/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive FIFO data full (RXI)
interrupts requested when the RDF flag or DR flag in
serial status register (SCFSR) is set to1, receive-error
(ERI) interrupts requested when the ER flag in SCFSR
is set to1, and break (BRI) interrupts requested when
the BRK flag in SCFSR or the ORER flag in line status
register (SCLSR) is set to1.
RXI interrupt requests can be cleared by reading the
DR or RDF flag after it has been set to 1, then clearing
the flag to 0, or by clearing RIE to 0. ERI or BRI
interrupt requests can be cleared by reading the ER,
BR or ORER flag after it has been set to 1, then
clearing the flag to 0, or by clearing RIE and REIE to 0.
0: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are disabled
1: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are enabled
5
TE
0
R/W Transmit Enable
Enables or disables serial transmission by the SCIF.
With TE set to 1, serial transmission starts when
transmit data is written to SCFTDR.
0: Transmission disabled
1: Transmission enabled*
Note: * Select the transmit format in SCSMR and
SCFCR and reset the transmit FIFO before
setting TE to 1.
Rev. 1.00 Sep. 19, 2007 Page 674 of 1136
REJ09B0359-0100