SH7730 Datasheet, PDF (476/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Table 12.5 Selecting External Request Detection by DL and DS Bits
CHCR_0, CHCR_1
DL
DS
0
0
1
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 12.6 Selecting External Request Detection with DO Bit
CHCR_0, CHCR_1
DO
0
1
External Request
Overrun 0
Overrun 1
(3) On-Chip Peripheral Module Request Mode
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
Transfer request signals are the transmit data empty transfer request and receive data full transfer
request from the SCIF0/1/2/3/4/5, IrDA0/1, SIOF, and SIM and transfer requests from the ADC
and CMT0/1/2/3/4, all of which are selected by DMARS0/1/2.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
Rev. 1.00 Sep. 19, 2007 Page 428 of 1136
REJ09B0359-0100