SH7730 Datasheet, PDF (249/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
31
20 19
14 13
87
210
Address field 1 1 1 1 0 1 1 0 0 0 0 0 * * * * * *
E
A* * * * *00
31
Data field
VPN
10 9 8 7
0
DV
ASID
VPN: Virtual page number
V: Validity bit
E: Entry
D: Dirty bit
*: Don't care
ASID: Address space identifier
A: Association bit
: Reserved bits (write value should be 0
and read value is undefined )
Figure 7.22 Memory-Mapped UTLB Address Array
7.7.5 UTLB Data Array (TLB Compatible Mode)
The UTLB data array is allocated to addresses H'F700 0000 to H'F70F FFFF in the P4 area. A
data array access requires a 32-bit address field specification (when reading or writing) and a 32-
bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array
are specified in the data field.
In the address field, bits [31:20] have the value H'F70 indicating UTLB data array and the entry is
specified by bits [13:8].
In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits
[6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates
WT.
The following two kinds of operation can be used on UTLB data array:
1. UTLB data array read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
2. UTLB data array write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
Rev. 1.00 Sep. 19, 2007 Page 201 of 1136
REJ09B0359-0100