SH7730 Datasheet, PDF (702/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.8 Interrupts
The SIOF has one type of interrupt.
(1) Interrupt Sources
Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR.
Table 21.14 lists the SIOF interrupt sources.
Table 21.14 SIOF Interrupt Sources
No. Classification
1 Transmission
2
3 Reception
4
5 Control
6
7 Error
8
9
10
11
12
Bit Name Function Name
Description
TDREQ
Transmit FIFO transfer The transmit FIFO empty area
request
exceeds specified size.
TFEMP Transmit FIFO empty The transmit FIFO is empty.
RDREQ Receive FIFO transfer The receive FIFO stores data of
request
specified size or more.
RFFUL Receive FIFO full
The receive FIFO is full.
TCRDY
Transmit control data The transmit control register is ready
ready
to be written.
RCRDY Receive control data The receive control data register
ready
stores valid data.
TFUDF
Transmit FIFO
underflow
Serial data transmit timing has arrived
while the transmit FIFO is empty.
TFOVF
Transmit FIFO overflow Write to the transmit FIFO is
performed while the transmit FIFO is
full.
RFOVF
Receive FIFO overflow Serial data is received while the
receive FIFO is full.
RFUDF
Receive FIFO
underflow
The receive FIFO is read while the
receive FIFO is empty.
FSERR FS error
A synchronous signal is input before
the specified bit number has been
passed (in slave mode).
SAERR Assign error
The same slot is specified in both
serial data and control data.
Rev. 1.00 Sep. 19, 2007 Page 654 of 1136
REJ09B0359-0100