SH7730 Datasheet, PDF (719/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
4
OE
0
R/W Parity Mode
Selects even or odd parity when parity bits are added
and checked. The OE setting is used only in
asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking.
The OE setting is ignored in clock synchronous mode, or
in asynchronous mode when parity addition and
checking is disabled.
0: Even parity*¹
1: Odd parity*²
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an even number of
1s in the received character and parity bit
combined.
2. If odd parity is selected, the parity bit is
added to transmit data to make an odd
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an odd number of 1s
in the received character and parity bit
combined.
Rev. 1.00 Sep. 19, 2007 Page 671 of 1136
REJ09B0359-0100