SH7730 Datasheet, PDF (467/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
7
DL
0
R/W DREQ Level and DREQ Edge Select
6
DS
0
R/W Specify the detecting method of the DREQ pin input.
These bits are valid only in CHCR_0 and CHCR_1.
Even in channels 0 and 1, also, if the transfer request
source is specified as an on-chip peripheral module or if
an auto-request is specified, these bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5
TB
0
R/W Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
4, 3
TS[1:0] 00
R/W DMA Transfer Size Specify
See the description of TS[3:2] (bits 21 and 20).
2
IE
0
R/W Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request (DEI)
to the CPU when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Rev. 1.00 Sep. 19, 2007 Page 419 of 1136
REJ09B0359-0100