SH7730 Datasheet, PDF (806/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
(1) Data Transfer Format
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.
(2) Clock
An internal clock generated by the on-chip baud rate generator or an external clock input through
the SCK pin can be selected as the serial clock for the SCIFA, according to the setting of the
CKE[1:0] bits in SCASCR.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed, the clock is fixed high. However, when the operation mode is
reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the
clock high every time one character is transferred, write to SCAFTDR the same number of
dummy data bytes as the data bytes to be received and set the TE and RE bits to 1 at the same time
to transmit the dummy data. When the specified number of data bytes are transmitted, the clock is
fixed high.
(3) Data Transfer Operations
(a) SCIFA Initialization
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCASCR to
0, then initialize the SCIFA as described below.
When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, SCATSR is initialized.
Note that clearing the TE and RE bits to 0 does not change the contents of SCASSR, SCAFTDR,
or SCAFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the
TEND bit in SCASSR has been set to 1. The TE bit should not be cleared to 0 during
transmission; if attempted, the TXD pin will go to the high-impedance state. Before setting TE to
1 again to start transmission, the TFRST bit in SCAFCR should first be set to 1 to reset
SCAFTDR.
Rev. 1.00 Sep. 19, 2007 Page 758 of 1136
REJ09B0359-0100