SH7730 Datasheet, PDF (222/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1)
7.4.1 Unified TLB (UTLB) Configuration
Figure 7.11 shows the configuration of the UTLB in TLB extended mode. Figure 7.12 shows the
relationship between the page size and address format.
Entry 0
Entry 1
Entry 2
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
Entry 63 ASID[7:0] VPN[31:10] V
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
Figure 7.11 UTLB Configuration (TLB Extended Mode)
[Legend]
• VPN: Virtual page number
For 1-Kbyte page: Upper 22 bits of virtual address
For 4-Kbyte page: Upper 20 bits of virtual address
For 8-Kbyte page: Upper 19 bits of virtual address
For 64-Kbyte page: Upper 16 bits of virtual address
For 256-Kbyte page: Upper 14 bits of virtual address
For 1-Mbyte page: Upper 12 bits of virtual address
For 4-Mbyte page: Upper 10 bits of virtual address
For 64-Mbyte page: Upper 6 bits of virtual address
• ASID: Address space identifier
Indicates the process that can access a virtual page.
In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH
bit is 0, this identifier is compared with the ASID in PTEH when address comparison is
performed.
• SH: Share status bit
When 0, pages are not shared by processes.
When 1, pages are shared by processes.
• ESZ: Page size bits
Specify the page size.
Rev. 1.00 Sep. 19, 2007 Page 174 of 1136
REJ09B0359-0100