SH7730 Datasheet, PDF (44/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Table 12.6
Table 12.7
Table 12.8
Table 12.9
Selecting External Request Detection with DO Bit .............................................. 428
Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 429
Supported DMA Transfers.................................................................................... 434
Relationship between Request Modes and Bus Modes by DMA Transfer
Category................................................................................................................ 439
Section 13 Clock Pulse Generator (CPG)
Table 13.1 Pin Configuration and Functions of CPG ............................................................. 452
Table 13.2 Clock Operating Modes ........................................................................................ 453
Table 13.3 Register Configuration.......................................................................................... 453
Table 13.4 Register States in Each Operating Mode .............................................................. 453
Table 13.5 Pairs of Power Supply Pins................................................................................... 463
Section 14 Reset and Power-Down Modes
Table 14.1 States of Power-Down Modes .............................................................................. 466
Table 14.2 Pin Configuration.................................................................................................. 466
Table 14.3 Register Configuration.......................................................................................... 467
Table 14.4 Register States in Each Operating Mode .............................................................. 467
Section 15 RCLK Watchdog Timer (RWDT)
Table 15.1 Register Configuration of RWDT......................................................................... 484
Table 15.2 Register State of RWDT in Each Operating Mode............................................... 484
Section 16 16-Bit Timer Pulse Unit (TPU)
Table 16.1 TPU Functions ...................................................................................................... 490
Table 16.2 Pin Configuration.................................................................................................. 492
Table 16.3 Register Configuration.......................................................................................... 493
Table 16.4 Register States in Each Operating Mode .............................................................. 496
Table 16.5 TPU Clock Sources............................................................................................... 498
Table 16.6 Counter Clock Selection by the TPSC[2:0] Bits................................................... 499
Table 16.7 Settings for Bits IOA[2:0], Initial States of Pin TPU0_TO0 to
TPU0_TO3, and Results of Matching with TPU0_TGRA ................................... 502
Table 16.8 Settings for Bits IOA[2:0], Initial States of Pin TPU1_TO0 and TPU1_TO1,
and Results of Matching with TPU1_TGRA........................................................ 502
Table 16.9 Register Combinations in Buffer Operation ......................................................... 513
Section 17 Realtime Clock (RTC)
Table 17.1 Pin Configuration.................................................................................................. 521
Table 17.2 Register Configuration of RTC............................................................................. 521
Table 17.3 Register State of RTC in Each Operating Mode................................................... 522
Rev. 1.00 Sep. 19, 2007 Page xliv of xlviii