SH7730 Datasheet, PDF (1028/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
Bit
Bit Name
29 to 24 MFI
Initial
Value
100000
23 to 16 AIV
All 0
15
—
0
14 to 12 SZ
All 0
11 to 8 —
All 0
R/W Description
R/W Match Flag Specify
Specifies the match flag to be included in the match
conditions.
000000: MF0 bit of the CCMFR register
000001: MF1 bit of the CCMFR register
Others: Reserved (setting prohibited)
Note: The initial value is the reserved value, but when 1
is written into CBR0[0], MFI must be set to 000000
or 000001. And note that the channel 0 is not hit
when MFE bit of this register is 1 and MFI bits are
000000 in the condition of CCRMF.MF0 = 0.
R/W ASID Specify
Specifies the ASID value to be included in the match
conditions.
R Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
R/W Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
conditions; thus, not checked (any operand size
specifies the match condition).*¹
001: Byte access
010: Word access
011: Longword access
100: Quadword access*²
Others: Reserved (setting prohibited)
R Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
Rev. 1.00 Sep. 19, 2007 Page 980 of 1136
REJ09B0359-0100