SH7730 Datasheet, PDF (1154/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
SIOF_SCK (input)
SIOF_SYNC (input)
SIOF_TXD
SIOF_RXD
t_FSS
t_FSH
t_STDD
t_SICYC
t_SWHI t_SWLI
t_STDD
t_SRDS t_SRDH
Figure 33.51 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2)
33.4.13 SCIF Module Signal Timing
Table 33.15 SCIF Module Signal Timing
Conditions: V_CCQ = 3.0 to 3.6 V, V_CC = 1.1 to 1.3 V, AV_CC = 3.0 to 3.6 V, T_a = -20 to 75°C
Item
Symbol
Min.
Max.
Input clock Asynchronous t
Scyc
cycle
Synchronous
12

4

Input clock rise time
t
SCKr
Input clock fall time
t_SCKf
Input clock pulse width
t
SCKW
Transmit data delay time
t
TXD
Receive data setup time
t
RXS
(synchronous)


0.4

2 t_Pcyc*
1.5
1.5
0.6
3
t
Pcyc
*+
50

Receive data hold time
t_RXH
2 t_Pcyc*

(synchronous)
RES delay time
t_RTSD

100
CTS setup time (clock time)
t_CTSS
100

CTS hold time (clock time)
t
CTSH
100

Note:
*
t
Pcyc
is
the
cycle
time
of
the
peripheral
clock
(Pφ).
Unit
t
Pcyc
t
Scyc
ns
Figure
33.52
33.53
33.52
33.53
Rev. 1.00 Sep. 19, 2007 Page 1106 of 1136
REJ09B0359-0100