SH7730 Datasheet, PDF (870/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
Initial
Bit
Bit Name Value R/W Description
5
TE
0
R/W Transmit Enable
Enables/disables serial transmit operations.
0: Disables transmission*¹
1: Enables transmission*²*³
Notes: 1. The TDRE flag in SCSSR is fixed to 1.
2. In this state, if transmit data is written to
SCTDR, the transmit operation is initiated.
Before setting the TE bit to 1, the serial mode
register (SCSMR) and smart card mode
register (SCSCMR) must always be set, to
determine the transmit format.
3. Even if the TE bit is cleared to 0, the ERS
flag is unaffected, and the previous state is
retained.
4
RE
0
R/W Receive Enable
Enables/disables serial receive operations.
0: Disables reception*¹
1: Enables reception*²
Notes: 1. Clearing the RE bit to 0 has no effect on the
RDRF, PER, ORER, or WAIT_ER flag, and
the previous state is retained.
2. If the start bit is detected in this state, serial
reception is initiated. Before setting the RE
bit to 1, SCSMR and SCSCMR must always
be set, to determine the receive format.
3
WAIT_IE 0
R/W Wait Enable
Enables/disables wait error interrupt requests.
0: Disables wait error interrupt (ERI) requests
1: Enables wait error interrupt (ERI) requests
Rev. 1.00 Sep. 19, 2007 Page 822 of 1136
REJ09B0359-0100