SH7730 Datasheet, PDF (650/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
20.4.7 Example of Use
Flowcharts in respective modes that use the I²C bus interface are shown in figures 20.14 to 20.17.
Start
Initialize
Read BBSY in ICCR2
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1
Write 1 to BBSY
and 0 to SCP
Write transmit data
in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Yes
Read ACKBR in ICIER
ACKBR=0 ?
No
Yes
Transmit
No
mode?
Yes
Write transmit data in ICDRT
Read TDRE in ICSR
No
TDRE=1 ?
Yes
No
Last byte?
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Yes
Clear TEND in ICSR
Clear STOP in ICSR
Write 0 to BBSY
and SCP
Read STOP in ICSR
No
STOP=1 ?
Yes
Set MST and TRS
in ICCR1 to 0
Clear TDRE in ICSR
End
[1] Test the status of the SCL and SDA lines.
[2] Set master transmit mode.
[1]
[3] Issue the start condition.
[4] Set the first byte (slave address + R/W) of transmit data.
[2]
[5] Wait for 1 byte to be transmitted.
[3]
[6] Test the acknowledge transferred from the specified slave device.
[4]
[7] Set the second and subsequent bytes (except for the final byte) of transmit data.
[8] Wait for ICDRT empty.
[5]
[9] Set the last byte of transmit data.
[6]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
Master receive mode
[7]
[12] Clear the STOP flag.
[13] Issue the stop condition.
[8]
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Figure 20.14 Sample Flowchart for Master Transmit Mode
Rev. 1.00 Sep. 19, 2007 Page 602 of 1136
REJ09B0359-0100