SH7730 Datasheet, PDF (1064/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 31 User Debugging Interface (H-UDI)
Table 31.4 Register States in Each Operating Mode
Register
Abbreviation
SDIR
SDDR/SDDRH
SDDRL
SDINT
Power-On Reset Software Standby Module Standby Sleep
H'0EFF
Retained
Retained
Retained
Undefined
Retained
Retained
Retained
Undefined
Retained
Retained
Retained
H'0000
Retained
Retained
Retained
31.3.1 Instruction Register (SDIR)
SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial
input (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state and can be written by
the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command
is set to this register.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI[7:0]
————————
Initial value: 0
0
0
0
1
11
0
1
1
1
1
1
1
1
1
R/W: R
R
R
RR
RR
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 8 TI
7 to 0 
Initial Value R/W
B'00001110 R
All 1
R
Description
Test Instruction Bits 7 to 0
01100000: H-UDI reset negate
01110000: H-UDI reset assert
10100000: H-UDI interrupt
00001110: Initial state
Other than above: Setting prohibited
Reserved
These bits are always read as 1.
Rev. 1.00 Sep. 19, 2007 Page 1016 of 1136
REJ09B0359-0100