SH7730 Datasheet, PDF (214/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR)
When the specific resource is changed, IRMCR controls whether the instruction fetch is
performed again for the next instruction. The specific resource means the part of control registers,
TLB, and cache.
In the initial state, the instruction fetch is performed again for the next instruction after changing
the resource. However, the CPU processing performance will be lowered because the instruction
fetch is performed again for the next instruction every time the resource is changed. Therefore, it
is recommended that each bit in IRMCR is set to 1 and the specific instruction should be executed
after all necessary resources have been changed prior to execution of the program which uses
changed resources.
For details on the specific sequence, see descriptions in each resource.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R2 R1 LT MT MC
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 5 
Initial
Value
All 0
4
R2
0
R/W Description
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W Re-Fetch Inhibit 2 after Register Change
When MMUCR, PASCR, CCR, PTEH, or RAMCR is
changed, this bit controls whether re-fetch is performed
for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Rev. 1.00 Sep. 19, 2007 Page 166 of 1136
REJ09B0359-0100