SH7730 Datasheet, PDF (1122/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
T_h
T₁
T_wx
T₂
T_f
CKO
t_AD1
t_AD1
A25 to A0
CSn
WEn
RDWR
Read _RD
D15 to D0
Write
RDWR
D15 to D0
BS
DACKn*
WAIT
t_CSD1
t_WED2
t_CSD1
t_WED2
t_RWD1
t_RSD
t_RWD1
t_RSD
t_RDS1
t_RDH1
t_RWD1
t_RWD1
t_WDD1
t_BSD
t_BSD
t_WDH1
t_DACD
t_WTH1
t_WTH1
t_DACD
t_WTS1
t_WTS1
Note: * Waveform when active low is specified for DACKn.
Figure 33.14 Bus Cycle of SRAM with Byte Selection
(CSnWCR.SW[1:0]=B'01, CSnWCR.HW[1:0]=B'01, External Wait 1 Input,
BAS = 1 (WE in Write Cycle Controlled))
Rev. 1.00 Sep. 19, 2007 Page 1074 of 1136
REJ09B0359-0100